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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs4952/53 ntsc/pal digital video encoder features l simultaneous composite and s-video output l supports rs170a and ccir601 composite output timing l multi-standard support for ntsc-m, pal (b, d, g, h, i, m, n, combination n) l optional progressive scan @ mpeg2 field rates l ccir656 input mode supporting eav/sav codes and ccir601 master/slave input modes l stable color subcarrier for mpeg2 systems l ntsc closed caption encoder with interrupt l supports macrovision copy protection in cs4953 version l host interface configurable for parallel or i 2 c compatible operation l general purpose input and output pins l individual dac power-down capability l on-chip voltage reference generator l on-chip color bar generator l +5 volt only, cmos, low power modes, tri-state dacs description the cs4952/3 provides full conversion from ycbcr or yuv digital video formats into ntsc & pal composite and y/c (s-video) analog video. input formats can be 27 mhz 8-bit yuv, 8-bit ycbcr, or ccir656 with sup- port for eav/sav codes. output video can be formatted to be compatible with ntsc-m, or pal b,d,g,h,i,m,n, and combination n systems. also supported is ntsc line 21 and line 284 closed captioning encoding. four 9-bit dacs provide two channels for an s-video out- put port and two composite video outputs. 2x oversampling reduces the output filter requirements and guarantees no dac related modulation components within the spec- ified bandwidth of any of the supported video standards. parallel or high speed i 2 c compatible control interfaces are provided for flexibility in system design. the parallel interface doubles as a general purpose i/o port when the cs4952/3 is in i 2 c mode to help conserve valuable board area. ordering information cs4952/3-cl 44 pin plcc cs4952/3-cq 44 pin tqfp clk scl sda pdat[7:0] rd* wr* addr xtal vd[7:0] hsync* vsync* field int reset* c cvbs37 cvbs75 y vrefin vrefou t iset vaa gnd test i c interface 2 host parallel interface color sub-carrier synthesizer video formatter video timing generator control registers output interpolate chroma amplifier chroma modulate burst insert chroma interpolate luma delay luma amplifier sync insert 9-bit dac voltage reference current reference 8 8 lpf lpf output interpolate lpf 9-bit dac 9-bit dac 9-bit dac s u, v y oct 97 ds223pp2
cs4952/53 2 ds223pp2 table of contents ac & dc parametric specifications .....................................................................4 introduction ...............................................................................................................11 functional description .........................................................................................11 video timing generator .........................................................................................11 video input formatter .............................................................................................11 color subcarrier synthesizer ..................................................................................12 chroma path ..........................................................................................................12 luma path ..............................................................................................................12 digital to analog converters ...................................................................................13 voltage reference ..................................................................................................13 current reference ..................................................................................................13 host interface .........................................................................................................13 closed caption services ........................................................................................13 control registers ....................................................................................................13 operational description .......................................................................................14 reset hierarchy ......................................................................................................14 video timing ...........................................................................................................14 slave mode input interface .............................................................................14 master mode input interface ...........................................................................14 vertical timing .................................................................................................15 horizontal timing ............................................................................................15 ntsc interlaced ..............................................................................................17 pal interlaced .................................................................................................17 progressive scan ............................................................................................19 pal progressive scan ....................................................................................19 ntsc progressive scan .................................................................................19 ccir-656 ................................................................................................................19 digital video input modes .......................................................................................22 multi-standard output format modes .....................................................................22 subcarrier generation ............................................................................................22 subcarrier compensation .......................................................................................22 closed caption insertion ........................................................................................23 color bar generator ...............................................................................................23 interrupts ................................................................................................................24 general purpose i/o port .......................................................................................24 analog ........................................................................................................................ ...24 analog timing .........................................................................................................24 vref ......................................................................................................................25 iset ........................................................................................................................25 dacs ......................................................................................................................25 luminance dac ..............................................................................................25 chrominance dac ..........................................................................................25 cvbs75 dac ..................................................................................................26 cvbs37 dac ..................................................................................................26 programming ..............................................................................................................27 host control interface .............................................................................................27 i2c interface ....................................................................................................27 8-bit parallel interface .....................................................................................27 register description ...............................................................................................28 control register 0 ............................................................................................28 control register 1 ............................................................................................29 control register 2 ............................................................................................30 dac power down register ..............................................................................30 status register.................................................................................................31 background color register ..............................................................................31 gpio control register .....................................................................................31 gpio data register .........................................................................................32 chroma filter register .....................................................................................32 luma filter register .........................................................................................32 i2c address register .......................................................................................32 subcarrier amplitude register .........................................................................33
cs4952/53 ds223pp2 3 subcarrier synthesis register ......................................................................... 33 hue lsb adjust register ................................................................................. 33 hue msb adjust register ................................................................................ 33 closed caption enable register...................................................................... 34 closed caption data register ......................................................................... 34 interrupt enable register ................................................................................. 34 interrupt clear register.................................................................................... 35 device id register ........................................................................................... 35 board design & layout considerations ......................................................... 36 power and ground planes ..................................................................................... 36 power supply decoupling ...................................................................................... 36 vref decoupling ................................................................................................... 36 digital interconnect ................................................................................................ 36 analog interconnect ............................................................................................... 37 analog output protection ....................................................................................... 37 esd protection ....................................................................................................... 37 external dac output filter ..................................................................................... 37 device pinout - 44 plcc ............................................................................................ 38 plcc pin description ............................................................................................ 39 device pinout - 44 tqfp ............................................................................................ 41 tqfp pin description ............................................................................................ 42
cs4952/53 4 ds223pp2 ac & dc parametric specifications absolute maximum ratings: (agnd, dgnd = 0 v, all voltages with respect to 0 v.) warning: operating beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions: (agnd, dgnd = 0 v, all voltages with respect to 0 v.) parameter symbol min max units power supply v aa -0.3 6.0 v input current per pin except supply pins -10 10 ma output current per pin except supply pins -50 +50 ma analog input voltage -0.3 v aa +0.3 v digital input voltage -0.3 v aa +0.3 v ambient temperature power applied -55 +125 c storage temperature -65 +150 c parameter symbol min typmax units power supplies: digital analog v aa 4.75 5.0 5.25 v operating ambient temperature t a 0+25+70 c
cs4952/53 ds223pp2 5 d.c. characteristics: (t a =25 c; v aa = 5 v; gnd = 0 v.) notes: 1. output current levels with iset = 10 k w , vrefin = 1.232 v. 2. times for black-to-white level and white-to-black level transitions. parameter symbol min typ max units digital inputs high level input voltage v [7:0], pdat [7:0], hsync /vsync /field/clkin v ih 2.0 - v aa +0.3 v high level input voltage i 2 c v ih 0.7v aa --v low level input voltage all inputs v il -0.3 - 0.8 v input leakage current digital inputs - -10 - +10 m a digital outputs high level output voltage io = -4ma v oh 2.4 - v aa v low level output voltage io = 4ma v ol --0.4v low level output voltage sda pin only, io = 6ma v ol --0.4v output leakage current high-z digital outputs - -10 - +10 m a analog outputs full scale output current cvbs37/y/c (note 1) io37 32.9 34.7 36.5 ma full scale output current cvbs75 (note 1) io75 16.4 17.3 18.2 ma lsb current cvbs37/y/c (note 1) ib37 64.5 68 71.5 m a lsb current cvbs75 (note 1) ib35 32.2 34 35.8 m a dac-to-dac matching mat - 2 - % output compliance v oc 0-+1.4v output impedance r out -15-k w output capacitance c out --30pf dac output delay o del -412ns dac rise/fall time (note 2) t rf -2.55ns voltage reference reference voltage output v ov 1.198 1.232 1.272 v reference input current i vc --10 m a power supply supply voltage v aa 4.75 5 5.25 v supply current all dacs on cvbs75/cvgs37 only cvbs75 only i aa 1 i aa 2 i aa 3 - - - 180 110 75 200 - - ma ma ma
cs4952/53 6 ds223pp2 d.c. characteristics (continued) parameter symbol min typ max units static performance dac resolution - - 9 bits differential non-linearity dnl -1 0.5 +1 lsb integral non-linearity inl -1 0.35 +1 lsb dynamic performance differential gain db - 2 5 % differential phase dp - 0.5 2 signal to noise ratio snr -70 - - db hue accuracy h a --2 saturation accuracy s a --2%
cs4952/53 ds223pp2 7 a.c. characteristics: t ch t cl t isu t ih t oa clk v[7:0] hsync*/vsync* (inputs) hsync*/vsync*/ cb/field/int (outputs) figure 1. video pixel data and control port timing parameter symbol min typ max units pixel input and control port clock pulse high time t ch 14.82 18.52 22.58 ns clock pulse low time t cl 14.82 18.52 22.58 ns clock to data set-up time t isu 6--ns clock to data hold time t ih 0--ns clock to data output delay t oa --17ns parameter symbol min typ max units i 2 c host port timing scl frequency f clk 100 1000 khz clock pulse high time t sph 0.1 s clock pulse low time t spl 0.7 s hold time (start condition) t sh 100 ns setup time (start condition) t ssu 100 ns data setup time t sds 50 ns rise time t sr 1s fall time t sf 0.3 s setup time (stop condition) t ss 100 ns bus free time t buf 100 ns data hold time t dh 0ns scl low to data out valid t vdo 600 ns figure 2. i 2 c host port timing sda scl t sh t sr t spl t sf t ssu t sph t sds t sh t ss t buf t vdo t dh
cs4952/53 8 ds223pp2 a.c. characteristics: (continued) addr pdat[7:0] t rdh t as t rpw t rda t rah t rd rd* addr pdat[7:0] t as t wpw wr* t wds t wr t wdh t wac rd* wr* t rec t rec parameter symbol min typ max units 8-bit parallel host interface read cycle time t rd 60 - - ns read pulse width t rpw 30 - - ns address setup time t as 3--ns read address hold time t rah 10 - - ns read data access time t rda --40ns read data hold time t rdh 10 - 50 ns write recovery time t wr 60 - - ns write pulse width t wpw 40 - - ns write data setup time t wds 8--ns write data hold time t wdh 3--ns write-read/read-write recovery time t rec 50 - - ns address from write hold time t wac 0--ns 8-bit parallel host port timing: read cycle 8-bit parallel host port timing: address write cycle 8-bit parallel host port timing: read-write/write-read cycle figure 3.
cs4952/53 ds223pp2 9 t res reset* a.c. characteristics: (continued) parameter symbol min typ max units reset timing reset pulse width t res 100 ns figure 4. reset timing
cs4952/53 10 ds223pp2 +5v (vcc) 4.7 f 0.1 f l1 ferrite bead xtal addr pdat[7:0] rd* wr* sda scl clk v[7:0] field hsync*/cb vsync* test gnd vaa vrefout vrefin cvbs75 cvbs37 y c int reset* iset gpio port 18 19 8 31 32 35 36 +5v (vcc) 1.5k w 1.5k w 110 w 110 w i c controller 2 27 mhz clock pixel data 8 33 0.1 f 75 w to rf modulator 75 w composite video connector 75 w 75 w s-video connector 10 k w 1% 2 21 22 38 cs4952 cs4953 nc 1 3 20 29 7-14 15 16 17 6 40 37 34 44 43 4 5 41 42 figure 5. typical connection diagram (i 2 c host interface)
cs4952/53 ds223pp2 11 introduction the cs4952/3 is a complete multi-standard digital video encoder implemented in current 5-volt only cmos technology. ccir601 or ccir656 compli- ant digital video input can be converted into ntsc-m, pal b, pal d, pal g, pal h, pal i, pal m, pal n, or pal n argentina-compatible analog video. the cs4952/3 is designed to connect to mpeg1 and mpeg2 digital video decompres- sors without glue logic. two 9-bit dac outputs provide high quality s-video analog output while two other 9-bit dacs simultaneously generate composite analog video. the cs4952/3 will accept 8-bit ycbcr or 8-bit yuv input data. the cs4952/3 is completely configured and con- trolled via an 8-bit host interface port or an i 2 c compatible serial interface. this host port provides access and control of all cs4952/3 options and fea- tures like closed caption insertion, interrupts, etc. in order to lower the end user set-top overall sys- tem costs, the cs4952/3 provides an internal volt- age reference which eliminates the requirement for an external discrete 3-pin voltage reference. functional description in the following subsections, the functions of the cs4952/3 will be described. the descriptions refer to the block diagram on the cover page. video timing generator all timing generation is accomplished via a 27 mhz input applied to the clk pin. the cs4952/3 can also accept an optional color burst crystal on the addr & xtal pins. see section: color subcarrier synthesizer (page 12), for further details. the video timing generator is responsible for or- chestrating most all of the other modules in the de- vice. it works in harmony with external sync input timing or by providing external sync timing out- puts. it automatically disables color burst on appro- priate scan lines and generates serration and equalization pulses on appropriate scan lines. the cs4952/3 is designed to function as a video timing master or video timing slave. in both master and slave modes, all timing is sampled and assert- ed with the rising edge of the clk pin. in most cases the cs4952/3 will serve as the video timing master. the master timing cannot be exter- nally altered other than through the host interface by changing the video display modes: pal or ntsc and progressive scan. hsync , vsync and field are configured as outputs for master mode. hsync can also be defined as a composite blanking output signal in master mode. exact hor- izontal and vertical display timing is addressed in section: operational description (page 14). in slave mode hsync and vsync are config- ured as input pins and are used to initialize inde- pendent vertical and horizontal timing generators upon their respective falling edges. field remains an output in slave mode. the cs4952/3 also provides a ccir-656 slave mode where the video input stream contains eav and sav codes. in this case, proper hsync vsync timing is extracted automatically without aid from any inputs other than the v [7:0]. ccir-656 input data is sampled with the leading edge of clk. slave mode vertical and horizontal timing derived via ccir-656 or external hardware must be equivalent to timing generated by the cs4952/3 in master mode. video input formatter the video input formatter translates ycbcr input data into yuv information, if necessary, and splits the luma and chroma information for filtering, scal- ing, and modulation.
cs4952/53 12 ds223pp2 color subcarrier synthesizer the subcarrier synthesizer is a digital frequency synthesizer that produces the correct subcarrier fre- quency for ntsc or pal. the cs4952/3 generates the color burst frequency based on the input clk (27 mhz). color burst accuracy and stability are limited by the accuracy of the 27 mhz input. if the frequency varies then the color burst frequency will also vary accordingly. in order to handle situations in which the clk var- ies unacceptably, a local crystal frequency refer- ence may be used on the addr & xtal device pins. in this instance the input clk is continuously compared with the external crystal reference input and the internal timing of the cs4952/3 is automati- cally adjusted so that the color burst frequency re- mains close to the requirements. controls are provided for phase adjustment of the burst to permit color adjustment and phase com- pensation. chroma hue control is provided by the cs4952/3 via a 10-bit hue control register (hue_lsb and h_msb). burst amplitude control is also made available to the host via the 8-bit burst amplitude register (sc_amp). chroma path the video input formatter at conclusion delivers 4:2:2 yuv outputs into separate chroma and luma data paths. the chroma path will be discussed here. the chroma output of the video input formatter is directed to a chroma low pass 19-tap fir filter. the filter bandwidth is selected or the filter may be by- passed via the control_1 register. the pass- band of the filter is either 650 khz or 1.3 mhz and the passband ripple is less than or equal to 0.05 db. the stopband for the 1.3 mhz selection begins at 3 mhz with an attenuation of greater that 35 db. the stopband for the 650 khz selection begins around 1.1 mhz with an attenuation of greater than 20 db. the output of the chroma low pass filter is connect- ed to the chroma interpolation filter where upsam- pling from 4:2:2 to 4:4:4 is accomplished. the chroma digital data is fed to a quadrature modulator where they are combined with the output from the subcarrier synthesizer to produce the proper modu- lated chrominance signal. following chroma modulation the chroma data passes through a variable gain amplifier where the chroma amplitude may be varied via the c_amp 8-bit host addressable register. the chroma then is interpolated by a factor of 2 in order to operate the output dacs at 2 times the pixel rate. the interpo- lated filters help reduce the sinx/x roll-off for high- er frequencies and reduce the complexity of the external analog low pass filters. luma path along with the chroma output path, the cs4952/3 video input formatter initiates a parallel luma data path by directing the luma data to a digital delay line. the delay line is built as a digital fifo where the depth of the fifo replicates the clock period delay associated with the more complex chroma path. following the luma delay, the data is passed through a variable gain amplifier where the luma dc values are modifiable via the y_amp register. the output of the luma amplifier connects to the sync insertion block. sync insertion is accom- plished by multiplexing into the luma data path the different sync dc values at the appropriate times. the digital sync generator takes horizontal sync and vertical sync timing signals and generates the appropriate composite sync timing (including ver- tical equalization and serration pulses), blanking information, and burst flag. the sync edge rates conform to rs-170a or ccir specifications. the luma only path is concluded via output interpo- lation by a factor of two in order to operate the out- put dacs at two times the pixel rate.
cs4952/53 ds223pp2 13 digital to analog converters the cs4952/3 provides four complete simulta- neous 27 mhz dacs for analog video output: one 9-bit for s-video chrominance, one 9-bit for s-vid- eo luminance, and two 9-bit composite outputs. both s-video dacs are designed for 37.5 w over- all loads. the two composite 9-bit dacs are not identical. one dac is designed to drive 37.5 w de- rived from a double terminated 75 w circuit. the second 9-bit dac is targeted for an on-board local video connection where single point 75 w termina- tion is sufficient i.e. ch3/4 rf modulators, video amps, muxes. the dacs can be put into tri-state mode via host addressable control register bits. each of the four dacs has its own separate dac enable associated with it. in the disable mode, the 9-bit dacs source or sink zero current. for lower power standby scenarios the cs4952/3 also provides power shut-off control for the dacs. each dac has a separate dac shut-off associated with it. voltage reference the cs4952/3 is equipped with an on-board 1.235 v voltage reference generator used by the video dacs. for most requirements, the voltage reference output pin can be connected to the volt- age reference input pin along with a decoupling ca- pacitor. otherwise the voltage reference input may be connected to an external voltage reference. current reference the dac output current per bit is derived in the current reference block. the current step is speci- fied by the size of resistor place between the iset current reference pin and electrical ground. this has been optimized for 10k w (see iset on page 25 for more informmation on selecting the proper iset value). host interface the cs4952/3 provides a parallel 8-bit data inter- face for overall configuration and control. the host interface uses active low read and write strobes along with an active low address enable signal to provide microprocessor compatible read and write cycles. indirect host addressing to the cs4952/3 in- ternal registers is accomplished via an internal ad- dress register which is uniquely accessible via bus write cycles with the host address enable signal as- serted. the cs4952/3 also provides an i 2 c compatible se- rial interface for device configuration and control. this port can operate in standard or fast (400 khz) modes. when in i 2 c mode, the parallel data inter- face pdat [7:0] pins may be used as a general pur- pose i/o port controlled by the i 2 c interface. closed caption services the cs4952/3 supports the generation of ntsc closed caption services. line 21 and line 284 cap- tioning can be generated and enabled independent- ly via a set of control registers. when enabled, clock run-in, start bit, and data bytes are automati- cally inserted at the appropriate video lines. a con- venient interrupt interface simplifies the software interface between the host processor and the cs4952/3. control registers the control and configuration of the cs4952/3 is primarily accomplished through the control regis- ter block. all of the control registers are uniquely addressable via the internal address register. the control register bits are initialized during a chip re- set. see the detailed operation section of this data sheet for all of the individual register bit allocations, bit operational descriptions and initialization states.
cs4952/53 14 ds223pp2 operational description reset hierarchy the cs4952/3 is equipped with an active low asyn- chronous reset input pin reset . reset is used to initialize the internal registers and the internal state machines for subsequent default operation. see the electrical and timing specification section of this data sheet for specific cs4952/3 chip reset and power-on signaling timing requirements and re- strictions. all chip outputs are valid after a time pe- riod following reset pin low. when the reset pin is held low, the host interface in the cs4952/3 is disabled and will not respond to host initiated bus cycles. a reset initializes the cs4952/3 internal registers to their default values as described by table 5. in the default state, the cs4952/53 video dacs are dis- abled and the device is configured to internally pro- vide blue field video data to the dacs (any input data present on the v [7:0] pins is ignored). other- wise the cs4952/53 registers are configured for ntsc-m ccir601 output operation. at a mini- mum, the dac register (0x04) must be written (to enable the dacs) and the in_mode bit of the control_0 register (0x01) must be set (to en- able ccir601 data input on v [7:0]) for the cs4952/53 to become operational after reset. video timing slave mode input interface in slave mode, the cs4952/3 takes vsync and hsync as inputs. slave mode is the default fol- lowing a reset and is changed to master mode via a contol register bit (control_0 [4]). the cs4952/3 is limited to ccir601 horizontal and vertical input timing. all clocking in the cs4952/3 is generated from the clk pin. in slave mode the sync generator uses externally provided horizontal and vertical sync signals to synchronize the internal timing of the cs4952/3. video data that is sent to the cs4952/3 must be synchronized to the horizontal and vertical sync signals. figure 6 illustrates horizontal timing for ccir601 input in slave mode. note that the cs4952/3 expects to receive the first active pixel data on clock cycle 245 (ntsc) when bit sync_dly=0 in the control_2 register (ox02). when sync_dly=1, it expects the first active pixel data on clock cycle 246 (ntsc). master mode input interface the cs4952/3 defaults to slave mode following reset high but may be switched into master mode via the mstr bit in the control_0 reg- ister (0x00). in master mode, the cs4952/3 uses the vsync , hsync and field device pins as clk 1706 active pixel #720 hsync* (input) v[7:0] (sync_dly=0) 1705 1704 1703 1728 1 2 3 128 129 264 265 266 267 268 1686 1685 1684 1683 1716 1 2 3 128 129 244 245 246 247 248 ycry cb y cr y horizontal blanking active pixel #1 active pixel #2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ntsc 27mhz clock count pal 27mhz clock count 1702 1682 active pixel #720 v[7:0] (sync_dly=1) ycry cb y cr horizontal blanking active pixel #1 active pixel #2 cb active pixel #719 figure 6. ccir601 input slave mode horizontal timing
cs4952/53 ds223pp2 15 outputs to schedule the proper external delivery of digital video into the v [7:0] pins. figure 7 illus- trates horizontal timing for ccir601 input in mas- ter mode. note that the cs4952/3 expects to receive the first active pixel data on clock cycle 245 (ntsc) when bit sync_dly=0 in the control_2 register (0x02). when sync_dly=1, it expects the first active pixel data on clock cycle 246 (ntsc). vertical timing the cs4952/3 can be selected through the control_0 register (0x00) to operate in four different timing modes: pal which is 625 vertical lines 25 frames per second interlaced, ntsc which is 525 vertical lines 30 frames per second interlaced and both pal and ntsc again but in progressive scan where the display is non-interlaced. the cs4952/3 conforms to standard digital decom- pression dimensions and does not process digital input data for the active analog video half lines as they are typically in the over/underscan region of televisions. for ntsc, 240 active lines total per field are processed and for pal 288 active lines to- tal per field. frame vertical dimensions are 480 lines for ntsc and 576 lines for pal. table 1 specifies active line numbers for both ntsc and pal. refer to figure 8 for hsync , vsync and field signal timing. table 1. vertical timing horizontal timing hsync is used to synchronize the horizontal input to output timing in order to provide proper horizon- tal alignment. hsync defaults to an input pin fol- lowing reset but switches to output in master mode (control_0 [4] = 1). horizontal timing is referenced to hsync transitioning low. for active video lines, digital video input is to be applied to the v [7:0] inputs 244 (ntsc) or 264 (pal), clk periods following hsync going low to determine the horizontal alignment of the active video. clk 1706 active pixel #720 hsync* (output) v[7:0] (sync_dly=0) 1705 1704 1703 1728 1 2 3 128 129 264 265 266 267 268 1686 1685 1684 1683 1716 1 2 3 128 129 244 245 246 247 248 ycry cb y cr y horizontal blanking active pixel #1 active pixel #2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ntsc 27mhz clock count pal 27mhz clock count cb* (output) 1702 1682 active pixel #720 v[7:0] (sync_dly=1) ycry cb y cr horizontal blanking active pixel #1 active pixel #2 active pixel #719 cb figure 7. ccir601 input master mode horizontal timing mode field active lines ntsc 1, 3 2, 4 22-261 285-524 pal 1, 3, 5, 7 2, 4, 6, 8 23-310 336-623 ntsc progressive-scan na 22-261 pal progressive-scan na 23-310
cs4952/53 16 ds223pp2 ntsc vertical timing (odd field) line hsync* vsync* field 3 4 5 6 7 8 9 10 ntsc vertical timing (even field) line hsync* vsync* field pal vertical timing (odd field) line hsync* vsync* field pal vertical timing (even field) line hsync* vsync* field 264 265 266 267 268 269 270 271 265 1 2 3 4 5 6 7 311 312 313 314 315 316 317 318 figure 8. vertical timing
cs4952/53 ds223pp2 17 ntsc interlaced the cs4952/3 supports ntsc-m and pal-m modes where there are 525 total lines per frame and two fixed 262.5 line fields per frame and 30 total frames occuring per second. please reference fig- ure 9 for ntsc interlaced vertical timing. each field consists of 1 line for closed caption, 240 ac- tive lines of video plus 21.5 lines of blanking. vsync field one transistions low at the beginning of line 4 and will remain low for 3 lines or (858 x 3) 2574 pixel cycles. the cs4952/3 exclusively re- serves line 21 of field one for closed caption inser- tion. digital video input is expected to be delivered to the cs4952/3 v [7:0] pins for 240 lines begin- ning on active video lines 22 and continuing through line 261. vsync field two transistions low in the middle of line 266 and stays low for 3 lines times and transitions high in the middle of line 269. the cs4952/3 exclusively reserves line 284 of field two for closed caption insertion. video input on the v [7:0] pins is expected between lines 285 through line 525. pal interlaced the cs4952/3 supports pal modes b, d, g, h, i, n, and combination n where there are 625 total lines per frame and two fixed 312.5 line fields per frame and 25 total frames occuring per second. please reference figure 10 for pal interlaced ver- tical timing. each field consists of 288 active lines of video plus 24.5 lines of blanking. figure 9. ntsc video interlaced timming 523 524 525 1 2 3 4 5 6 7 8 9 vsync* drops 10 22 analog field 1 261 262 263 analog field 2 285 284 272 271 270 269 268 267 266 265 264 523 524 525 1 2 3 4 5 6 7 8 9 vsync* drops 10 22 analog field 3 261 262 263 analog field 4 285 284 272 271 270 269 268 267 266 265 264 burst begins with positive half-cycle burst begins with negative half-cycle
cs4952/53 18 ds223pp2 621 622 623 analog field 1 burst phase = 135 degrees relative to u burst phase = 225 degrees relative to u 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 2 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 3 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 4 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 5 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 6 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 7 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 8 308 311 312 313 314 315 316 317 318 319 320 336 337 vsync* drops figure 10. pal video interlaced timing
cs4952/53 ds223pp2 19 vsync will transition low to begin field one and will remain low for 2.5 lines or (864 x 2.5) 2160 pixel cycles. digital video input is expected to be delivered to the cs4952/3 v [7:0] pins for 287 lines beginning on active video line 24 and continu- ing through line 310. field two begins with vsync transitioning low after 312.5 lines from the beginning of field one. vsync stays low for 2.5 lines times and transi- tions high with the beginning of line 315. video in- put on the v [7:0] pins is expected between line 336 through line 622. progressive scan the cs4952/3 supports a progessive scan mode where the video output is non-interlaced. this is accomplished by displaying only the first video field for ntsc or pal. to preserve exact mpeg-2 frame rates of 30 and 25 per second, the cs4952/3 displays the same first field repetitively but alter- nately varies the field times. other digital video en- coders commonly support progressive scan by repetitively displaying a 262 line field (524/525 lines for ntsc). in the long run this method is flawed in that over time, the output display rate will overrun a system clock locked mpeg-2 decom- pressor and display a field twice every 8.75 sec- onds. pal progressive scan vsync will transistion low to begin field one and will remain low for for 2.5 lines or (864 x 2.5) 2160 pixel times. please reference figure 11 for pal non-interlaced timing. digital video input is ex- pected to be delivered to the cs4952/3 v [7:0] pins for 288 lines beginning on active video line 23 and continuing through line 309. field two begins with vsync transitioning low after 312 lines from the beginning of field one. vsync stays low for 2.5 line times and transitions high during the middle of line 315. video input on the v [7:0] pins is expected between line 335 through line 622. field two is 313 lines long while field one is 312. ntsc progressive scan vsync will transition low at line 4 to begin field one and will remain low for 3 lines or (858 x 3) 2574 pixel times. please reference figure 12 for ntsc interlaced timing. digital video input is ex- pected to be delivered to the cs4952/3 v [7:0] pins for 240 lines beginning on active video line 22 and continuing through line 261. field two begins with vsync transitioning low at line 266. vsync stays low for 2.5 line times and transitions high during the middle of line 268. vid- eo input on the v [7:0] pins is expected between line 284 through line 524. field two is 263 lines long while field one is 262. ccir-656 the cs4952/3 supports an additional slave mode feature that is selectable through the ccir601 bit of the control_0 register. the ccir-656 slave feature is unique because the horizontal and verti- cal timing and digital video are combined into a single 8-bit 27 mhz input. with ccir-656 there are no horizontal and vertical input or output strobes, only 8-bit 27 mhz active cbycry data with start and end of video codes being implement- ed with reserved 00 and ff code sequences within the video feed. as with all modes, v [7:0] are sam- pled with the rising edge of clk. the cs4952/3 expects the digital ccir-656 stream to be error free. the field output toggles as with non ccir-656 input. ccir-656 input timing is illus- trated in figure 13.
cs4952/53 20 ds223pp2 309 310 311 analog field 1 burst phase = 135 degrees relative to u burst phase = 225 degrees relative to u 312 313 1 2 3 4 5 6 7 23 24 309 analog field 2 308 311 312 vsync* drops 12345 6 7 23 24 310 309 310 311 analog field 3 312 313 1 2 3 4 5 6 7 23 24 309 analog field 4 308 311 312 12345 6 7 23 24 310 figure 11. pal video non-interlaced progressive scan timing
cs4952/53 ds223pp2 21 261 262 1 23456 789 start of vsync 10 22 field 1 burst begins with positive half-cycle burst begins with negative half-cycle burst phase = reference phase = 180 relative to b-y 0 burst phase = reference phase = 180 relative to b-y 0 262 263 1 23456 78910 22 261 262 1 23456 78910 22 262 263 1 23456 78910 22 field 2 field 3 field 4 start of vsync figure 12. ntsc video non-interlaced progressive scan timing composite video v[7:0] active video y cr y ff 10 xy 00 eav code 4 clocks 00 80 10 80 10 80 10 80 80 10 80 10 80 10 ff xy 00 00 cb y cr cb y cr ancilliary data 268 clocks (ntsc) 280 clocks (pal) horizontal blanking sav code 4 clocks active video 1440 clocks ccir656 data figure 13. ccir656 input mode timing
cs4952/53 22 ds223pp2 digital video input modes the cs4952/3 provides 2 different digital video in- put modes that are selectable through the in_mode bit of the control_0 register. in mode 0 and upon reset, the cs4952/3 defaults to output a solid color (1 of a possible of 256 col- ors). the background color is selected by writing the bkg_color register (0x08). the colorspace of the register is rgb 3:3:2 and is unaffected by gamma correction. the default color following re- set is blue. in mode 1 the cs4952/3 supports a single 8-bit 27 mhz cbycry source as input on the v [7:0] pins. input video timing can be ccir601 master or slave and progressive scan. multi-standard output format modes the cs4952/53 supports a wide range of output formats compatible with worldwide broadcast stan- dards. these formats include ntsc-m, pal-b/d/g/h/i, pal-m, pal-n and pal combi- nation n (pal-nc) which is the broadcast standard used in argentina. after reset, the cs4952/53 de- faults to ntsc-m operation with ccir601 analog timing. ntsc-m can also be supported in the japa- nese format by turning off the 7.5 ire pedestal through the ped bit in the control_1 register (0x01). output formats are configured by writing control registers as shown in table 2. subcarrier generation the cs4952/3 automatically synthesizes ntsc and pal color subcarrier clocks using the clk fre- quency and four control registers (sc_synth0/1/2/3). the ntsc subcarrier syn- thesizer is reset every four fields and every eight fields for pal. the sc_synth0/1/2/3 registers used together provide a 32-bit value which defaults to ntsc val- ues of 43e0f83eh following reset. table 3 indicates the 32-bit value required for the different broadcast formats. subcarrier compensation since the subcarrier is synthesized from clk the subcarrier frequency error will track the clock fre- quency error. if the input clock has a tolerance of 200 ppm then the resulting subcarrier will also have a tolerance of 200 ppm. per the ntsc speci- fication the final subcarrier tolerance is 10 hz which is more like 3 ppm. care must be taken in se- lecting a suitable clock source. in mpeg-2 system environments the clock is actu- ally recovered from the data stream. in these cases the recovered clock can be 27 mhz 50 ppm or address register ntsc-mc cir601 ntsc-mcci r60 (japan) ntsc-mr s170a pal-b,d, g,h,i pal-m pal-n pal-ncom (argentina) 0x00 control_0 01h 01h 21h 41h 61h a1h 81h 0x01 control_1 04h 00h 04h 04h 04h 04h 04h 0x10 sc_amp 1ch 1ch 1ch 15h 15h 15h 15h 0x11 sc_synth0 3eh 3eh 3eh 96h 4eh 96h 8ch 0x12 sc_synth1 f8h f8h f8h 15h 4ah 15h 28h 0x13 sc_synth2 e0h e0h e0h 13h e1h 13h edh 0x14 sc_synth3 43h 43h 43h 54h 43h 54h 43h table 2. multi-standard format register configurations (slave mode, interlaced timing, non-656 data)
cs4952/53 ds223pp2 23 1350 hz. it varies per television but in many cases given an mpeg-2 system clock of 27 mhz 1350 hz the resultant color subcarrier produced will be outside of the televisions ability to compen- sate and the chrominance information will not be displayed (black and white picture only). the cs4952/3 is designed to provide automatic compensation for an excessively inaccurate mpeg-2 system clock. sub-carrier compensation is enabled through the xtal bit of the control_2 register. when enabled the cs4952/3 will utilize a common quartz color burst crystal (3.579545 mhz 50 ppm for ntsc) at- tached to the addr and xtal pins to automati- cally compare and compensate the color subcarrier synthesis process. use of the addr and xtal pins requires that the host interface is configured for i 2 c operation. closed caption insertion the cs4952/3 is capable of ntsc closed caption insertion on lines 21 and 284 independently. closed captioning is enabled for either or both lines 21 & 284 via the cc_en [1:0] register bits and data to be inserted is also written into the four closed caption data registers. the cs4952/3 when en- abled automatically generates the seven cycles of clock run-in (32 x line rate), start bit insertion (001)and finally insertion of the two data bytes per line. data low at the video outputs corresponds to 0 ire and data high corresponds to 50 ire. there are two independent 8-bit registers per line (cc_21_1 & cc_21_2 for line 21 and cc_284_1 & cc_284_2 for line 284). interrupts are also pro- vided to simplify the handshake between the driver software and the chip. typically the host would write all 4 bytes to be inserted into the registers and then enable closed caption insertion and interrupts. as the closed caption interrupts occur the host soft- ware would respond by writing the next two bytes to be inserted to the correct control registers and then clear the interrupt and wait for the next field. color bar generator the cs4952/3 is equipped with a color bar genera- tor that is enabled through the cbar bit of the control_1 register. the color bar generator works in master or slave mode and has no effect on the video input/output timing. if the cs4952/3 is configured for slave mode color bars, proper video timing must be present on the hsync and vsync pins for the color bars to be displayed. given proper slave mode input timing or master mode, the color bar generator will override the vid- eo input pixel data. the output of the color bar generator is instantiated after the chroma interpolation filter and before the luma delay line. the generated color bar numbers are for 100% amplitude, 100% saturation ntsc eia color bars or 100% amplitude, 100% satura- tion pal ebu color bars. for pal color bars, the cs4952/3 generates ntsc color bar values, which are very close to standard pal values. the exact luma and chroma values are listed in table 4. system fsubcarrier value (dec) value (hex) ntsc-m 3.5795455 mhz 1138817086 43e0f83e pal-b, d, g, h, i, n 4.43361875 mhz 1410536854 54131596 pal-n (argentina) 3.582056 mhz 1139615885 43ed288d pal-m 3.579611 mhz 1138838095 43cddfc7 table 3. multi-standard format fsc register configurations
cs4952/53 24 ds223pp2 table 4. internal color bar values (8-bit values, cb/cr are in 2s complement format) interrupts in order to better support precise video mode switches and to establish a software/hardware handshake with the closed caption insertion block the cs4952/3 is equipped with an interrupt pin named int. the int pin is active high. there are three interrupt sources: vsync , line 21 and line 284. each interrupt can be individually disabled with the int_en register. each interrupt is also cleared via writing a one to the corresponding int_clr register bits. the three individual inter- rupts are ored together to generate an interrupt signal which is presented on the int output pin. if an interrupt has occurred, it cannot be eliminated with a disable, it must be cleared. general purpose i/o port the cs4952/53 has a gpio port and register which is available when the device is configured for i 2 c host interface operation. in i 2 c host interface mode, the pdat [7:0] pins are unused by the host interface and they may operate independently as in- put or output pins for the gpio_data_reg reg- ister (0x0a). the cs4952/53 also contains the gpio_ctrl_reg register (0x09) which is used to configure the gpio pins for input or output op- eration. the gpio port pdat [7:0] pins are configured for input operation when the corresponding gpio_ctrl_reg [7:0] bits are cleared. in gpio input mode, the cs4952/53 will latch the data on the pdat [7:0] pins into the corresponding bit lo- cations of gpio_data_reg when it detects reg- ister address 0x0a through the i 2 c interface. a detection of address 0x0a can happen in two ways. the first and most common way this will happen is when address 0x0a is written to the cs4952/53 via its i 2 c interface. the second method for detecting address 0x0a is implemented by accessing register address 0x09 through i 2 c. in i 2 c host interface op- eration, the cs4952/53 register address pointer will auto-increment to address 0x0a after an address 0x09 access. the gpio port pdat [7:0] pins are configured for output operation when the corresponding gpio_ctrl_reg [7:0] bits are set. in gpio out- put mode, the cs4952/53 will output the data in gpio_data_reg [7:0] bit locations onto the corresponding pdat [7:0] pins when it detects a register address 0x0a through the i 2 c interface. analog analog timing all cs4952/3 analog timing and sequencing is de- rived from the 27 mhz clock input. the analog out- puts are controlled internally by the video timing generator in conjunction with master and slave tim- ing. the video output signals perform accordingly for ntsc, pal specifications and both modes again but with progressive scan non-interlaced video out- put. being that the cs4952/3 is almost entirely a digital circuit, great care has been taken to guarantee ana- log timing and slew rate performance as specified in the ntsc and pal analog specifications. refer- ence the analog parameters section of this data sheet for exact performance parameters. color cb cr y white 0 0 +180 yellow -84 +14 +162 cyan +28 -84 +131 green -56 -70 +112 magenta +56 +70 +84 red -28 +84 +69 blue +84 -14 +35 black 0 0 +16
cs4952/53 ds223pp2 25 vref the cs4952/3 can operate with or without the aid of an external voltage reference. the cs4952/3 is designed with an internal voltage reference genera- tor that provides a vrefout signal. the internal voltage reference is utilized by electrically con- necting the vrefout and vrefin pins. vre- fin can also be connected to an external precision 1.235 volt reference. in either case, vrefin is to be decoupled to ground with a 0.1 m f capacitor. decoupling should be applied as close to the device pin as possible. iset all four of the cs4952/3 digital to analog converter dacs are output current normalized with a com- mon iset device pin. the dac output current per bit is determined by the size of the resistor connect- ed between iset and electrical ground. typically a 10 k w 1% metal film resistor should be used. the iset resistance can be changed by the user to ac- commodate varying video output attenuation via post filters and also to suit individual preferred per- formance. in conjunction with the iset value, the user may also independently vary the chroma, luma and col- orburst amplitude levels via host addressable con- trol register bits that are used to control internal digital amplifiers. the dac output levels are de- fined by the following operations: vrefin/riset = iref 1.235 v/10 k w = 123.5 a cvbs37/y/c outputs: vout (max) = iref (8/15) 511 37.5 w = 1.262 v cvbs75 output: vout (max) = iref (4/15) 511 75 w = 1.262 v dacs the cs4952/3 is equipped with 4 independent vid- eo grade current output digital to analog converters. they are 9-bit dacs operating at a 27 mhz two times oversampling rate. all four dacs are dis- abled and put in a low power mode upon reset. all four dacs can be individually powered down and disabled. the output current per bit of all four dacs is determined by the size of resistor connect- ed between the iset pin and electrical ground. luminance dac the y pin is driven from a 9-bit 27 mhz current output dac that internally receives the y or lumi- nance portion of the video signal (black and white intensity and syncronization information only). y is designed to drive proper video levels into a 37.5 w load. reference the detailed electrical sec- tion of this data sheet for the exact y digital to an- alog ac and dc performance data. a y_en enable control bit in the dac register (0x08) is provided to enable or disable the luminance dac. for a complete disable and lower power operation the luminance dac can be totally shut down via the y_pd control bit in the dac register (0x08). in this mode turn-on through the control register will not be instantaneous. chrominance dac the c pin is driven from a 9-bit 27 mhz current output dac that internally receives the c or chrominance portion of the video signal (color only). c is designed to drive proper video levels into a 37.5 w load. reference the detailed electrical section of this data sheet for the exact c digital to analog ac and dc performance data. a c_en en- able control register bit in the dac register (0x08) is provided to enable or disable the chrominance dac. for a complete disable and lower power op- eration the chrominance dac can be totally shut down via the c_pd control register bit in the dac
cs4952/53 26 ds223pp2 register (0x08). in this mode turn-on through the control register will not be instantaneous. cvbs75 dac the cvbs75 pin is driven from a 9-bit 27 mhz current output dac that internally receives a com- bined luma and chroma signal to provide compos- ite video output. cvbs75 is designed to drive proper composite video levels into a 75 w load. reference the detailed electrical section of this data sheet for the exact cvbs75 digital to analog ac and dc performance data. a c_75_en enable con- trol register bit in the dac register (0x08) is provid- ed to enable or disable the ouput pin. when disabled, no current flows from the output. for a complete disable and lower power operation the cvbs75 dac can be totally shut down via the c_75_pd control register bit in the dac register (0x08). in this mode turn-on through the control register will not be instantaneous. cvbs37 dac the cvbs37 pin is driven from a 9-bit 27 mhz current output dac that internally receives a com- bined luma and chroma signal to provide compos- ite video output. cvbs37 is designed to drive proper composite video levels into a 37.5 w load. reference the detailed electrical section of this data sheet for the exact cvbs37 digital to analog ac and dc performance data. the c_37_en dac en- able control register bit is in the dac register (0x08) provided to enable or disable the ouput pin. when disabled, no current flow from the output. for a complete disable and lower power operation the cvbs37 dac can be totally shut down via the c_37_pd control register bit in the dac register (0x08). in this mode turn-on through the control register will not be instantaneous.
cs4952/53 ds223pp2 27 programming host control interface the cs4952/3 host control interface can be config- ured for i 2 c or 8-bit parallel operation. the cs4952/3 will default to i 2 c operation when the rd and wr pins are both tied low at power up. the rd and wr pins are active for 8-bit parallel oper- ation only. i 2 c interface the cs4952/3 provides an i 2 c interface for access- ing the internal control and status registers. external pins are a bidirectional data pin (sda) and a serial input clock (scl). the protocol follows the i 2 c specifications. a complete data transfer is shown in figure 14. note that this i 2 c interface will work in slave mode only - it is not a bus master. sda and scl are connected via an external pull-up resistor to a positive supply voltage. when the bus is free, both lines are high. the output stag- es of devices connected to the bus must have an open-drain or open-collector in order to perform the wired-and function. data on the i 2 c bus can be transferred at a rate of up to 400 kbits/sec in fast mode. the number of interfaces to the bus is solely dependent on the limiting bus capacitance of 400 pf. when 8-bit parallel interface operation is being used, sda and scl can be tied directly to ground. the i 2 c bus address for the cs4952/3 is program- mable via register i2c_adr (0x0f). 8-bit parallel interface the cs4952/3 is equipped with a full 8-bit parallel microprocessor write and read control port. along with the pdat [7:0] pins the control port interface is comprised of host read rd and host write wr active low strobes and host address enable addr which, when low, enables unique address register accesses. the control port is used to access internal registers which configure the cs4952/3 for various modes of operation. the internal registers are uniquely addressed via an address register. the ad- dress register is accessed during a host write cycle with the wr and addr pins set low. host write cycles with addr set high will write the 8-bits on the pdat [7:0] pins into the register currently se- lected by the address register. likewise read cycles occur with rd set low and addr set high will re- turn the register contents selected by the address register. reference the detailed electrical timing parameter section of this data sheet for exact host parallel interface timing characteristics and specifi- cations. when i 2 c interface operation is being used, rd and wr must be tied to ground. pdat [7:0] are available to be used for gpio op- eration in i 2 c host interface mode. sda scl i c protocol 2 start address r/w ack data stop a p 1-7 89 ack 1-7 89 data ack 1-7 89 note: i c transfers data always with msb first, lsb last 2 figure 14. i 2 c data transfer
cs4952/53 28 ds223pp2 register description a set of internal registers are available for control- ling the operation of the cs4952/3. the registers extend from internal address 0x00 through 0x3d. table 5 shows a complete list of these registers and their internal addresses. note that this table and the subsequent register description section describe the full register map for cs4952 only. a complete cs4953 register set description is only available to macrovision acp-ppv licensed buyers. address register name type default value 0x00 control_0 r/w 01h 0x01 control_1 r/w 04h 0x02 control_2 r/w 00h 0x03 reserved 0x04 dac r/w f0h 0x05 - 0x06 reserved 0x07 status read only 00h 0x08 bkg_color r/w 03h 0x09 gpio_ctrl_reg r/w 0x0a gpio_data_reg r/w 00h 0x0b - 0x0c reserved 0x0d c_amp r/w 80h 0x0e y_amp r/w 80h 0x0f i2c_adr r/w n/a 0x10 sc_amp r/w 1ch 0x11 sc_synth0 r/w 3eh 0x12 sc_synth1 r/w f8h 0x13 sc_synth2 r/w e0h 0x14 sc_synth3 r/w 43h 0x15 hue_lsb r/w 00h 0x16 hue_msb r/w 00h 0x17 reserved 0x18 cc_en r/w 00h 0x19 cc_21_1 r/w 00h 0x1a cc_21_2 r/w 00h 0x1b cc_284_1 r/w 00h 0x1c cc_284_2 r/w 00h 0x1d - 0x3a reserved 0x3b int_en r/w 00h 0x3c int_clr r/w 00h 0x3d id_reg read only n/a table 5. control register map
cs4952/53 ds223pp2 29 control register 0 address 0x00 control_0 read/write default value = 01h control register 1 address 0x01 control_1 read/write default value = 04h bit number76543210 bit name tv_fmt mstr ccir656 prog in_mode cbcr_uv default00000001 bit mnemonic function 7:5 tv_fmt selects the tv display format 000: ntsc-m ccir601 timing (default) 001: ntsc-m rs170a timing 010: pal-b, d, g, h, i 011: pal-m 100: pal-n (argentina) 101: pal-n (non argentina) 110-111: reserved 4 mstr 1: master mode, 0: slave mode 3 ccir656 video input is in ccir656 format (0: off, 1: on) 2 prog progressive scanning enable (enable with 1) 1 in_mode input select (0: solid background, 1: use v [7:0] data) 0 cbcr_uv enable ycbcr to yuv conversion (1: enable, 0: disable) bit number76543210 bit name cblank y_delay c_bw c_lpf_en fld ped cbar cbcrsel default00000100 bit mnemonic function 7 cblank composite blank / hsync output select (1: cb, 0: hsync) 6 y_delay luma to chroma delay (0: no delay, 1: luma is delayed by one 13.5 mhz cycle) 5 c_bw chroma lpf bandwidth (0: 650 khz, 1: 1.3 mhz) 4 c_lpf_en chroma lpf on/off (0: off, 1: on) 3 fld polarity of field (0: odd field - 0, 1: odd field - 1) 2 ped pedestal offset (0: 0 ire, 1: 7.5 ire) 1 cbar internal color bar generator (0: off, 1: on) 0 cbcrsel cbcr select (0: chroma undelayed, 1: chroma delayed by one clock)
cs4952/53 30 ds223pp2 control register 2 address 0x02 control_2 read/write default value = 00h dac power down register address 0x04 dac read/write default value = f0h bit number76543 210 bit name reserved sync_dly xtal sc_en default00000 000 bit mnemonic function 7:4 - reserved 3y_bw selects between 4.2 mhz and 6 mhz on-chip luminance low pass filters; default value is zero which selects the 4.2 mhz low pass filter option 2 sync_dly delays expected timing of first active pixel input data relative to falling edge of hsync from 245 27 mhz clock cycles to 246 for ntsc and from 265 to 266 for pal. default state is sync_dly=0 for no delay 1 xtal crystal oscillator for subcarrier adjustment enable (1: enable) 0 sc_en chroma burst disable (1: disable) bit number76543210 bit name c_75_pd c_37_pd y_pd c_pd c_75_en c_37_en y_en c_en default11110000 bit mnemonic function 7 c_75_pd power down composite dac with 75 w load (0: power up, 1: power down) 6 c_37_pd power down composite dac with 37.5 w load (0: power up, 1: power down) 5 y_pd power down luma s-video dac (0: power up, 1: power down) 4 c_pd power down chroma s-video dac (0: power up, 1: power down) 3 c_75_en enable composite video dac output for 75 w (0: tri-state, 1: enable) 2 c_37_en enable composite video dac output for 37.5 w (0: tri-state, 1: enable) 1 y_en enable s-video dac for luma output (0: tri-state, 1: enable) 0 c_en enable s-video dac for chroma output (0: tri-state, 1: enable)
cs4952/53 ds223pp2 31 status register address 0x07 status read only default value = 00h background color register address 0x08 bkg_color read/write default value = 03h gpio control register address 0x09 gpio_ctrl_reg read/write default value = 00h bit number76 5 4 3 210 bit name reserved cc_int_21 cc_int_284 vs_int field default 0 0 0 0 0 0 0 0 bit mnemonic function 7:6 - reserved 5 cc_int_21 interrupt flag for line 21 (closed caption) complete 4 cc_int_284 interrupt flag for line 284 (closed caption) complete 3 vs_int interrupt flag for video field change 2:0 field field status bits 000: field 8 001: field 1 010: field 2 011: field 3 100: field 4 101: field 5 110: field 6 111: field 7 bit number76543210 bit name bg_colr default00000011 bit mnemonic function 7:0 bg_colr background color (7:5 = r, 4:2 = g, 1:0 = b) bit number76543210 bit name gpio_io default00000000 bit mnemonic function 7:0 gpio_io input(0)/output(1) control of gpio registers (bit x: pdat(x) i/o configuration)
cs4952/53 32 ds223pp2 gpio data register address 0x0a gpio_data_reg read/write default value = 00h chroma filter register address 0x0d c_amp read/write default value = 80h luma filter register address 0x0e y_amp read/write default value = 80h i 2 c address register address 0x0f i2c_adr read/write default value = n/a bit number76543210 bit name gpio_data default00000000 bit mnemonic function 7:0 gpio_data gpio data register; data is output on pdat [7:0] bus if appropriate bit in gpio_ctrl_reg (0x09) is set to 1; data on pdat [7:0] is latched into gpio_data_reg [7:0] when register address 0x0a is accessed via i 2 c. this register is only accessible in i 2 c mode. bit number76543210 bit name c_coef default10000000 bit mnemonic function 7:0 c_coef chroma amplitude coefficient bit number76543210 bit name y_coef default10000000 bit mnemonic function 7:0 y_coef luma amplitude coefficient bit number7 6543210 bit name reserved addr default - ------- bit mnemonic function 7 - reserved 6:0 addr i 2 c device address (programmable)
cs4952/53 ds223pp2 33 subcarrier amplitude register address 0x10 sc_amp read/write default value = 1ch subcarrier synthesis register address 0x11 sc_synth0 read/write default value = 3eh 0x12 sc_synth1 f8h 0x13 sc_synth2 e0h 0x14 sc_synth3 43h hue lsb adjust register address 0x15 hue_lsb read/write default value = 00h hue msb adjust register address 0x16 hue_msb read/write default value = 00h bit number76543210 bit name amp default00011100 bit mnemonic function 7:0 amp color burst amplitude register bits mnemonic function sc_synth0 7:0 - subcarrier synthesis bits 7:0 sc_synth1 7:0 - subcarrier synthesis bits 15:8 sc_synth2 7:0 - subcarrier synthesis bits 23:16 sc_synth3 7:0 - subcarrier synthesis bits 31:24 bit number76543210 bit name lsb default00000000 bit mnemonic function 7:0 lsb 8 lsbs for hue phase shift bit number76543210 bit name reserved msb default00000000 bit mnemonic function 7:2 - reserved 1:0 msb 2 msbs for hue phase shift
cs4952/53 34 ds223pp2 closed caption enable register address 0x18 cc_en read/write default value = 00h closed caption data register address 0x19 cc_21_1 read/write default value = 00h 0x1a cc_21_2 00h 0x1b cc_284_1 00h 0x1c cc_284_2 00h interrupt enable register address 0x3b int_en read/write default value = 00h bit number76543210 bit name reserved en_284 en_21 default00000000 bit mnemonic function 7:2 - reserved 1 en_284 enable closed caption for line 284 0 en_21 enable closed caption for line 21 register bit mnemonic function cc_21_1 7:0 - first closed caption databyte of line 21 cc_21_2 7:0 - second closed caption databyte of line 21 cc_284_1 7:0 - first closed caption databyte of line 284 cc_284_2 7:0 - second closed caption databyte of line 284 bit number76543210 bit name reserved en_21 en_284 vs_en default00000000 bit mnemonic function 7:3 - reserved 2 en_21 interrupt enable for closed caption line 21 1 en_284 interrupt enable for closed caption line 284 0 vs_en interrupt enable for new field
cs4952/53 ds223pp2 35 interrupt clear register address 0x3c int_clr read/write default value = 00h device id register address 0x3d id_reg read only default value = n/a bit number76543210 bit name reserved clr_21 clr_284 vs_clr default00000000 bit mnemonic function 7:3 - reserved 2 clr_21 clear interrupt for closed caption line 21 (int_21) 1 clr_284 clear interrupt for closed caption line 284 (int_284) 0 vs_clr clear interrupt for new video field (int_v) bit number76543210 bit name dev_id reserved default 0 0 0 0 - - - - bit mnemonic function 7:4 dev_id 0000 device id for cs4952 0001 device id for cs4953 3:0 - these bits are reserved and the value they return on a read is not defined
cs4952/53 36 ds223pp2 board design & layout considerations the printed circuit layout should be optimized for lowest noise on the cs4952/3 power and ground lines. digital and analog sections should be physi- cally separated and the cs4952/3 placed as close to the output connectors as possible. all analog sup- ply traces should be as short as possible to mini- mize inductive ringing. a well designed power distribution network is es- sential in eliminating digital switching noise. the ground planes must provide a low-impedance re- turn path for the digital circuits. a pc board with a minimum of four layers is recommended. the ground layer should be used as a shield to isolate noise from the analog traces. the top layer (1) should be reserved for analog traces but digital traces may share this layer if the digital signals have low edge rates and switch little current or if they are separated from the analog traces by a sig- nificant distance (dependent on their frequency content and current). the second layer should then be the ground plane followed by the analog power plane on layer three and the digital signal layer on layer four power and ground planes the power and ground planes need isolation gaps of at 0.05 to minimize digital switching noise ef- fects on the analog signals and components. a split analog/digital ground plane should be connected at one point as close as possible to the cs4952/3. a split analog/digital power plane should be connect- ed at one point as close as possible to the power en- try point and decoupled properly. power supply decoupling start by reducing power supply ripple and wiring harness inductance by placing a large (33 - 100uf) capacitor as close to the power entry point as pos- sible. use separate power planes or traces for the digital and analog sections even if they use the same supply. if necessary, further isolate the digital and analog power supplies by using ferrite beads on each supply branch followed by a low esr capac- itor. place all decoupling caps as close as possible to the device as possible. surface mount capacitors gen- erally have lower inductance than radial lead or ax- ial lead components. surface mount caps should be placed on the component side of the pcb to mini- mize inductance caused by board vias. any vias, especially to ground, should be as large as practical to reduce their inductive effects. vref decoupling the vrefout pin provides a 1.235 v reference for the internal dacs. vrefout is only intended to drive vrefin. do not connect to an external load. a small bypass cap, however, may be placed on vrefout to reduce noise. usually a 0.1uf mlc surface mount capacitor is sufficient. digital interconnect the digital inputs and outputs of the cs4952/3 should be isolated from the analog outputs as much as possible. use separate signal layers whenever possible and do not route digital signals over the analog power and ground planes. noise from the digital section is directly related to the digital edge rates used. ringing, overshoot, un- dershoot, and ground bounce are all related to edge rate. use lower speed logic such as hcmos for the host port interface to reduce switching noise. for the video input ports, higher speed logic is re- quired, but use the slowest practical edge rate to re- duce noise. to reduce digital noise, it is important to match the source impedance, line impedance, and load im- pedance as much as possible. generally, if the line length is greater than one fourth the signal edge rate, line termination is necessary. ringing may also be reduced by damping the line with a series resistor (22 - 150 w ). under extreme cases, it may
cs4952/53 ds223pp2 37 be advisable to use microstrip techniques to further reduce radiated switching noise if very fast edge rates (<2ns) are used. if microstrip techniques are used, split the analog and digital ground planes and use proper rf decoupling techniques. analog interconnect the cs4952/3 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. all un- used analog outputs should be placed in shutdown. this reduces the total power that the cs4952/3 re- quires, and eliminates the impedance mismatch pre- sented by an unused connector. the analog outputs should not overlay the analog power plane to maxi- mize high frequency power supply rejection. analog output protection to minimize the possibility of damage to the ana- log out put sections, make sure that all video con- nectors are well grounded. the connector ground should have a good dc ground path to the analog and digital power supply grounds. if no dc (and low frequency) path is present, improperly ground- ed equipment may impose damaging reverse cur- rents on the video out lines. therefore, it is also a good idea to use output filters that are ac coupled to avoid any problems. esd protection external dac output filter if an output filter is required for the composite and/or s-video outputs of the cs4952/53, the fol- lowing low pass filter in figure 15 can be used. 2.2 m h 330pf 220pf out in c 1 c 2 c cable c 2 c 1 c cable should be chosen so that = c 2 + figure 15. low pass filter
cs4952/53 38 ds223pp2 cs4952/3-cl 44-pin plcc top view 18 20 22 24 26 28 1 2 4 640 42 44 12 8 10 14 16 7 9 11 13 15 17 29 31 33 35 37 39 34 30 32 36 38 vaa gnd vaa cvbs37 cvbs75 test v0 v1 v2 v3 v4 v5 v6 v7 field hsync/cb vsync xtal addr vaa gnd gnd c y vrefout vrefin iset vaa gnd reset scl sda int clkin wr rd pdat0 pdat1 pdat2 pdat3 pdat4 pdat5 pdat6 pdat7 device pinout - 44 plcc
cs4952/53 ds223pp2 39 plcc pin description pin name pin number type description v [7:0] 14, 13, 12, 11, 10, 9, 8, 7 in digital video data inputs clk 33 in 27 mhz input clock addr 19 in address enable line / subcarrier crystal input xtal 18 out subcarrier crystal output hsync /cb 16 i/o active low horizontal sync, or composite blank signal vsync 17 i/o active low vertical sync. field 15 out video field id. selectable polarity rd 31 in host parallel port read strobe, active low wr 32 in host parallel port write strobe, active low pdat [7:0] 23,24,25,26,27,28,29,30 i/o host parallel port/ general purpose i/o sda 35 i/o i 2 c data scl 36 in i 2 c clock input cvbs75 5 current composite video output for driving 75 w loads cvbs37 4 current composite video output for driving 37.5 w loads y 43 current luminance analog output for driving 37.5 w loads c 44 current chrominance analog output for driving 37.5 w loads vrefout 42 out internal voltage reference output vrefin 41 in external voltage reference input iset 40 out dac current set int 34 out interrupt output, active high reset 37 in active low master reset test 6 in test pin. ground for normal operation vaa 1, 3, 20, 39 ps +5 v supply gnd 2, 22, 21, 38 ps ground
cs4952/53 40 ds223pp2 inches millimeters dim min max min max a 0.165 0.180 4.043 4.572 a1 0.090 0.120 2.205 3.048 b 0.013 0.021 0.319 0.533 d 0.685 0.695 16.783 17.653 d1 0.650 0.656 15.925 16.662 d2 0.590 0.630 14.455 16.002 e 0.685 0.695 16.783 17.653 e1 0.650 0.656 15.925 16.662 e2 0.590 0.630 14.455 16.002 e 0.040 0.060 0.980 1.524 jedec # : ms-018 44l plcc package drawing d1 d e1 e d2/e2 b e a1 a
cs4952/53 ds223pp2 41 vaa gnd vaa cvbs37 cvbs75 test v0 v1 v2 v3 v4 v5 v6 v7 field hsync/cb vsync xtal addr vaa gnd gnd c y vrefout vrefin iset vaa gnd reset scl sda int clkin wr rd pdat0 pdat1 pdat2 pdat3 pdat4 pdat5 pdat6 pdat7 cs4952/3-cl 44-pin tqfp top view 12 40 42 44 34 36 38 6 2 4 8 10 1 3 5 7 9 11 28 32 30 26 24 33 31 29 27 25 23 14 16 18 20 22 device pinout - 44 tqfp
cs4952/53 42 ds223pp2 tqfp pin description pin name pin number type description v [7:0] 8, 7, 6, 5, 4, 3, 2, 1 in digital video data inputs clkin 27 in 27 mhz input clock addr 13 in address enable line / subcarrier crystal input xtal 12 out subcarrier crystal output hsync /cb 10 i/o active low horizontal sync, or composite blank signal vsync 11 i/o active low vertical sync. field 9 out video field id. selectable polarity rd 25 in host parallel port read strobe, active low wr 26 in host parallel port write strobe, active low pdat [7:0] 17,18,19,20,21,22,23,24 i/o host parallel port/ general purpose i/o sda 29 i/o i 2 c data scl 30 in i 2 c clock input cvbs75 43 current composite video output for driving 75 w loads cvbs37 42 current composite video output for driving 37.5 w loads y 37 current luminance analog output for driving 37.5 w loads c 38 current chrominance analog output for driving 37.5 w loads vrefout 36 out internal voltage reference output vrefin 35 in external voltage reference input iset 34 out dac current set int 28 out interrupt output, active high reset 31 in active low master reset test 44 in test pin. ground for normal operation vaa 14, 33, 39, 41 ps +5 v supply gnd 15, 16, 32, 40 ps ground
cs4952/53 ds223pp2 43 inches millimeters dim min max min max a 0.000 0.065 0.000 1.600 a1 0.002 0.006 0.050 0.150 b 0.012 0.018 0.300 0.450 d 0.478 0.502 11.700 12.300 d1 0.404 0.412 9.900 10.100 e 0.478 0.502 11.700 12.300 e1 0.404 0.412 9.900 10.100 e 0.029 0.037 0.700 0.900 l 0.018 0.030 0.450 0.750 0.000 7.000 0.000 7.000 jedec # : ms-026 44l tqfp package drawing e1 e d1 d 1 e l b a1 a

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